One of operation tests of the semiconductor device is a transition delay test (TDT) evaluating a delay. In the transition delay test, a signal pattern to generate a signal change upon application of clock is set in flip-flops in the semiconductor device that is a test object by a scan shift or the like, and two pulses (clocks) at high speed are applied from an external part. The clock application for the first time generates a signal change and the clock application for the second time captures the changed signal in an arbitrary flip-flop. By comparing and determining whether the captured changed signal coincides with an expected value, the determination whether the delay in the semiconductor device satisfies the condition as non-defective or not is performed. More specifically, in the transition delay test, when the changed signal coincides with the expected value, the semiconductor device is determined as non-defective, whereas when the changed signal does not coincide with the expected value, the semiconductor device is determined as defective. Causes of occurrence of defective include various ones such as the switching noise, the configuration of design for test (DFT), the measurement circumference, the transistor characteristics and so on.
Further, a semiconductor device in which a power supply noise measurement cell composed of a MOS transistor having a gate connected to a power supply noise measurement point in the semiconductor device, a source connected to a determination reference voltage supply terminal, and a drain connected to a measurement terminal is installed to enable measurement of the power supply noise is proposed. This semiconductor device supplies the determination reference voltage to the source via the determination reference voltage supply terminal and monitors, at the measurement terminal, the change in the drain current with respect to variation in a gate-source voltage or the change of the ON/OFF state according to the power supply noise to measure the power supply noise (see, for example, Patent Document 1).    [Patent Document 1] Japanese Laid-open Patent Publication No. 2004-184345
In the transition delay test, the test is conducted while the semiconductor device operates under conditions more strict than the actual use conditions such that the signal changes are generated in the flip-flops in the semiconductor device at the same time. In other words, the transition delay test is conducted while a number of flip-flops that is nearly impossible under the actual use conditions operate at the same time. Therefore, when the transition delay test is conducted in a large-size semiconductor device having a huge number of flip-flops, the semiconductor device may be determined, due to the influence of the generated noise, as defective which will be determined as non-defective without the influence of the noise. In other words, the delay increases due to the influence of the power supply noise (a drop of the power supply voltage) generated by the operation (switching relating to the signal change) or the like of the huge number of flip-flops, with the result that the semiconductor device may be determined as defective.